1. Field of the Invention
The present invention relates to a semiconductor device, more specifically to a semiconductor device having a plurality of chips stacked so as to implement a three-dimensional (3-D) configuration and a method of assembling the semiconductor device.
2. Description of the Related Art
With movement toward higher levels of integration and improved functions of electric devices in recent years, various assembling methods for 3-D chip stacking technology have been developed.
As a commonly used method for assembling a semiconductor device, a core board, which serves as an intermediate layer, is sandwiched between a lower-layer semiconductor package and an upper-layer semiconductor package. Then, the core board and the lower-layer and upper-layer semiconductor packages are fixed by use of thermo compression. The lower-layer and upper-layer semiconductor packages can be connected with a plurality of vias buried in the core board.
To improve electrical connection between the upper-layer and lower-layer semiconductor packages, a fluctuation of the height of the vias buried in the core board have to be suppressed. However, since the vias are formed by plating, a number of platings have to be processed to control the height of vias. This as a result, complicates manufacturing process and decreases manufacturability.
As another assembling method for the semiconductor device, the upper-layer and the lower-layer semiconductor packages are stacked and connected directly with a plurality of bumps without using the intermediate layer. However, since an alignment between the lower-layer and upper-layer semiconductor packages is difficult, a misalignment between the lower-layer and upper-layer semiconductor packages occurs.